As transistors become smaller, it is desirable to increase the charge carrier mobility in the channel region. Increasing charge carrier mobility increases the switching speed of the transistor. Channel regions formed from materials other than silicon have been proposed to increase charge carrier mobility. For example, conventional thin film transistors which typically utilize polysilicon channel regions have been formed on a silicon-germanium (Si—Ge) epitaxial layer above a glass (SiO2) substrate. The Si—Ge epitaxial layer can be formed by a technique in which a semiconductor thin film such as an amorphous silicon hydride (a-Si:H), an amorphous germanium hydride (a-Ge:H), or the like is melted and crystallized by the irradiation of pulse laser beams.
In a bulk type device such as a metal oxide semiconductor field effect transistor (MOSFET), the use of Si—Ge materials could be used to increase charge carrier mobility, especially hole-type carriers. A tensile-strained silicon channel region can have carrier mobility 2-5 times greater than a conventional Si channel region due to reduced carrier scattering and the reduced mass of holes in the germanium-containing material. According to conventional Si—Ge formation techniques for bulk-type devices, a dopant implant molecular beam epitaxy (MBE) technique forms a Si—Ge epitaxial layer. However, the MBE technique requires very complicated, very expensive equipment, and is not as desirable as other processes for mass production of ICs.
Double gate transistors, such as double gate silicon-on-insulator (SOI) transistors, have significant advantages related to high drive current and also exhibit high immunity to short channel effects. An article by Huang et al. entitled “Sub-50 nm FinFET: PMOS”, (1999 IEDM) discusses a silicon transistor in which the active layer is surrounded by a gate on two sides. However, double gate structures can be difficult to manufacture using conventional IC fabrication tools and techniques.
Heretofore, double gate transistors have been difficult to align. Misalignments between double gates can adversely affect the operation of the transistor. Further, it is desirable to form a strained channel double gate silicon-on-insulator transistor using process steps suitable for mass production of ICs. Yet further still, there is a need for a method of manufacturing a self-aligned double gate semiconductor-on-insulator transistor.
Thus, there is a need for an integrated circuit or electronic device that includes channel regions with higher channel mobility, higher immunity to short channel effects, and higher drive current. Further, there is a need for transistors with a strained channel region that can be more easily manufactured. Even further, there is a need for a method of manufacturing a double gate, fully depleted, semiconductor-on-insulator transistor. Yet further, there is a need for a method of fabricating a double gate transistor having a strained silicon channel. Yet even further, there is a need for an efficient method of manufacturing a double gate transistor having a strained channel.